Such a switching network is already known from Belgian patent no. 904100 (P. DEBUYSSCHER et al 3-5-1). Therein the switching element is an electrical bus and the control circuit periodically assigns a time slot to each input thereof which is used to transfer data to an output. Since with such a bus the path between an input and an output is not the same for all inputs and outputs, bit shifts may occur at high data bit rates, e.g. of the order of 500 Megabit/sec., so that the data then appearing at the outputs are no longer synchronized. Obviously this is undesirable and post transmission means are required to recover the synchronism.
Another drawback of such a bus is that the data transmission thereon occurs in two directions and that during this transmission the data have to pass the junction points of various inputs and outputs on the bus. In order to prevent electric reflections at the above mentioned high bit rates it is therefore necessary to correctly terminate this bus at both its ends and at each location of the inputs and outputs. However, such terminations can generally not be made ideal and therefore give rise to distortion of the data.